1. Technical Field
The present invention generally relates to circuit test structures, and in particular to test structures for testing data path cycle times and other functional operational characteristics of memory arrays. Still more particularly, the present invention relates to a test structure for characterizing production static random access memory (SRAM) arrays and register file memories in a manner that accounts for fabrication layout characteristics as well as circuit topology characteristics such as bitline loading without changing the structure or behavior of the production array.
2. Description of Related Art
Memory speed poses a major limitation to modern data processing systems. It has been predicted that memory speed will become even more of a critical limitation as processor technologies move forward. In order to bridge the significant processing cycle gaps between processors and system memories (typically made of dynamic random access memories), SRAMs are commonly used as cache memories within processors for fast access to data and instructions.
With technology scaling on SRAM cells, certain device parameters, such as threshold voltage, become more susceptible to process variations. In order to come up with an optimal design for an SRAM array, an SRAM designer must have a clear understanding of various process variations in the processing technology for manufacturing SRAM arrays. Such information can typically be gained by using a simple test circuit for characterizing SRAM arrays.
In order to have the best result when characterizing a SRAM array, a test structure should be able to mimic an operating condition very close to true bitline loading. Also, the test structure should have the device and interconnect layout characteristics of the SRAM cells within the SRAM array. In addition, any electric circuit for tracking the characteristics of local bitlines within the test structure should not add extraneous load on the local bitlines of the production SRAM array.
The present disclosure describes a test system for evaluating the cell, subarray and array performance of a production memory array using a proxy memory array test structure that substantially replicates the on-chip physical device and interconnection layout of the functional memory array and which is fabricated and operated under conditions that closely approximate local bitline loading characteristics of the production array.